Wojciech Muła:
The goal of this text is to provide an overview of RISC-V Vector extension (RVV), and compare — when applicable — with widespread SIMD vector instruction sets: SSE, AVX, AVX-512, ARM Neon and SVE.
The RISC-V architecture defines four basic modes (32-bit, 32-bit for embedded systems, 64-bit, 128-bit) and several extensions. For instance, the support for single precision floating-point numbers is added by the F extension.
The vector extension is quite a huge addition. It adds 302 instructions plus four highly configurable load & store operations. The RVV instructions can be split into three groups:
- related to masks,
- integer operations,
- and floating-point operations.
When a CPU does not support floating-point instructions, it still may provide the integer subset.
RVV introduces 32 vector registers v0, …, v31, a concept of mask (similar to AVX-512), and nine control registers.
Detailed, but not too long overview of the RISC-V vector extensions.